SINGAPORE — 11 MAY 2016, UNITED STATES–(Marketwired – May 10, 2016) –
STATS ChipPAC Pte. Ltd. (“STATS ChipPAC” or the “Company”), a leading provider of advanced semiconductor packaging and test services, announced today that it has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package.
As the industry was beginning to learn about eWLB in 2008, STATS ChipPAC immediately recognized the significant potential, value and scalability of eWLB and designated it as a key technology for the company. Within a year, STATS ChipPAC had ramped eWLB to high volume production and was driving a number of technology and manufacturing initiatives in this new packaging approach. STATS ChipPAC has led the industry in eWLB manufacturing capabilities, capacity and technology innovations, particularly in 2.5D and 3D package designs. STATS ChipPAC became the first company in the semiconductor industry to implement significantly larger than 300mm eWLB wafer manufacturing capabilities and has a strong portfolio of innovative eWLB packages, including small die, large die, multi-die, multi-layer, Package-on-Package (PoP) and System-in-Package (SiP) architectures.
“We differentiated STATS ChipPAC by our unwavering commitment to eWLB technology over the years, beginning with our vision of how this scalable packaging platform can be leveraged to drive performance and size advantages for our customers’ applications. Over the years we have made significant capital investments and process enhancements to fulfill our vision and raise the bar on manufacturing efficiency and productivity in the industry, adding further value for our customers,” said Dr. Han Byung Joon, President and Chief Executive Officer, STATS ChipPAC. “Although we have achieved multiple milestones with eWLB through the years, shipping over one billion eWLB packages is a testament to the ever expanding customer adoption in the industry and success which we knew was possible with this game changing technology.”
The exceptional success of eWLB in the mobile market, particularly in baseband processors, connectivity devices, Codec devices, RF transceivers and power management integrated circuits (PMICs), is a reflection of the ongoing pressure semiconductor companies face in cost effectively achieving higher input/output (I/O), higher bandwidths and lower power consumption in the smallest possible form factor. STATS ChipPAC has driven a number of eWLB technology achievements such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line width and spacing down to 2um/2um and ultra thin package profiles below 0.3mm (including solderball) for single packages and below 0.6mm for a stacked PoP with proven warpage control.
With the ability to partition silicon and embed passive devices and vertical interconnects (known as eBar) into a design, eWLB is a powerful integration technology for 2.5D and 3D PoP or SiP solutions for a wide range of new and emerging applications. The compelling performance, size and cost advantages of eWLB are accelerating the adoption of this advanced technology into new markets such as the Internet of Things (IoT) and wearable electronics, Micro-Electro-Mechanical Systems (MEMS) and automotive applications. Examples of new eWLB applications are Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market.
Forward-Looking Statements
Certain statements in this release, including statements regarding the Company’s expectations and intentions relating to the issue of the New Notes and use of proceeds thereof, are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chain; disruption of our operations and other difficulties related to the relocation of our China operations; loss of directors, key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; beneficial ownership of our ordinary shares by Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) which may have conflicting interests with other holders of our securities; our inability to capture all or any of the benefits from acquisitions and investments in other companies and businesses or from the acquisition of us by JCET; loss of customers or failure to compete effectively with our former Taiwan subsidiaries which we have recently divested; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; and natural calamities and disasters, including outbreaks of epidemics and communicable diseases. STATS ChipPAC does not intend, and does not assume any obligation to update any forward-looking statements to reflect subsequent events or circumstances. References to “$” are to the lawful currency of the United States of America.
About STATS ChipPAC Pte. Ltd.
STATS ChipPAC Pte. Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices throughout Asia, the United States and Europe. STATS ChipPAC is a business unit of Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET), a publicly-traded company on the Shanghai Stock Exchange. Further information is available at www.statschippac.com or www.cj-elec.com. Information contained in this website does not constitute a part of this release.
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